Computer:- A computer is characterized by the Input–Process–Output (IPO) cycle, in which it accepts input, processes the data, and produces output.
Introduction:-
NET-JUNE-2026
1. The average memory access time is 130 ns and average time of cache memory is 100 ns . With 75% hit ratio, The average time to access a word is ?
1. 130 ns
2. 150 ns
3. 132.5 ns
4. 107.5 ns
NET-JUNE-2026
2. A problem of size n requires n2 bit operations. What is the largest size instance that can be solved in 1 second, if each bit operation is carried out in 10-9 second ?
1. 109
2. 3.16 x 104
3. 3.96 x 107
4. 210^9
NET-JUNE-2026
3. Arrange the following in terms of their capacity from smallest to largest :
A. L3 Cache B. L1 Cache
C. CPU Register D. L2 Cache
Choose the correct answer from the options given below:
1. C, D, B, A
2. C, A, B, D
3. C, B, D, A
4. A, C, D, B
NET-JUNE-2026
4. What does "Amdahl's Law" describe in the context of parallel processing ?
1. Maximum speedup achievable, considering serial and parallel portions of a program
2. The efficiency of message passing in a distributed memory system
3. Computational efficiency of a parallel algorithm
4. The reliability of a fault tolerant system
NET-DEC-2025
Comprehension:
A system trasnfer data blocks of 2000 bytes with programmed I/O, each byte transfer takes 6 CPU cycles, with direct memory access (DMA), the block transfer takes 3000 Cycles total, with CPU setup overhead of 200 cycles. The CPU clock is 1 GHZ. Answer the following 5 questions based on this paragraph.
1. How much CPU time is consumed by programmed I/O ?
1. 12 µs
2. 20 µs
3. 24 µs
4. 30 µs
2. How much CPU time is consumed by DMA overhead ?
1. 0.2 µs
2. 2.0 µs
3. 3.0 µs
4. 12.0 µs
3. How many CPU cycles are spent with DMA ?
1. 200 Cycles
2. 3000 Cycles
3. 3200 Cycles
4. 4000 Cycles
4. Which is more CPU-efficient for large block transfer ?
1. Programmed I/O
2. DMA
3. Both Programmed I/O and DMA
4. Depends on block size
5. How many CPU cycles are spent using programmed I/O ?
1. 2000
2. 6000
3. 12000
4. 20000
NET-DEC-2024
1. Match the LIST-I with LIST-II
LIST-I | LIST-II | ||
A. | (100110011)2 | I. | Error detection code |
B. | Complements | II. | CISC |
C. | Parity Bits | III. | Negative number |
D. | Variable length instruction | IV. | (133)16 |
Choose the correct answer from the options given below:
1. A - IV, B - I, C - III, D - II
2. A - IV, B - III, C - I, D - II
3. A - IV, B - II, C - III, D - I
4. A - I, B - IV, C - II, D - III
NET-DEC-2024
2. Match the LIST-I with LIST-II
LIST-I | LIST-II | ||
A. | RAID level 1 | I. | bit-interleaved parity organization |
B. | RAID level 2 | II. | disk mirroring |
C. | RAID level 3 | III. | block-interleaved parity organization |
D. | RAID level 4 | IV. | ECC organization |
Choose the correct answer from the options given below:
1. A - II, B - I, C - IV, D - III
2. A - II, B - IV, C - I, D - III
3. A - III, B - IV, C - I, D - II
4. A - IV, B - III, C - II, D - I
NET-DEC-2024
3. Which are often needed to evaluate the cache performance ?
1. Hit Ratio
2. Latency
3. Cache Traces
4. Transfer Rate
NET-DEC-2024
4. Arrange the following in the increasing order with respect to access time.
A. Solid State Drive
B. Optical Disks
C. DRAMs
D. SRAMs
E. Registers
Choose the correct answer from the options given below:
1. D, C, A, B, E
2. B, D, C, A, E
3. A, E, B, D, C
4. E, D, C, A, B
NET-DEC-2024
5. Correct the order of instruction cycle:
A. Read the effective address
B. Fetch the information
C. Execute the instruction
D. Decode the instruction
Choose the correct answer from the options given below:
1. A, B, C, D
2. B, D, A, C
3. B, A, D, C
4. A, B, D, C
NET-DEC-2024
6. If the virtual memory size is 32 MB and a physical memory size is 4 MB with a page size of 2 KB, Calculate the number of frames available in physical memory.
1. 1024
2. 2048
3. 3072
4. 4096