Department of Engineering and Technological Studies, University of Kalyani
B.Tech. Pt-III (IT) 1st Semester Examination, 2025
Subject: Computer Organization & Architecture
Paper: IT504
Full marks=70 Time: 3 Hours
The figures in the right-hand margin indicate marks.
Candidates are required to give their answers in their own words as far as possible.
The notations follow their standard meanings.
Answer question number one and any five from rest.
1. Answer any ten questions: (2 x 10 = 20)
a) State the principle of locality of references.
b) Define instruction prefetching.
c) What, in general terms, is the distinction between computer architecture and computer organization?
d) Derive the range of an n-bit number using the 2’s-complement, and 1’s-complement number representations.
e) Explain memory address register (MAR) and instruction register (IR).
f) Why 2’s complement representation of a signed number is a better representation?
g) What are the difference between DRAM and SRAM.
h) What do you mean by seek time and rotational latency?
i) What are the write through and write back policy?
j) Explain temporal and spatial locality.
k) What are the differences between sequential access of memory and random access of memory?
l) What are the differences between Immediate Addressing and Direct Addressing?
m) Discuss Bus Interconnection Scheme.
n) Define parallel and serial interface.
o) What do you mean by Displacement Addressing?
2. a) State Amdahl’s Law.
b) Suppose that we want to enhance the processor used for Web serving. The new processor is 10 times faster on computation in the Web serving application than the original processor. Assuming that the original processor is busy with computation 40% of the time and is waiting for I/O 60% of the time, what is the overall speedup gained by incorporating the enhancement?
c) What do you mean by millions of instructions per second (MIPS) rate?
(2+5+3)
3. a) Suppose that the processor has access to two levels of memory. Level 1 contains 1000 words and has an access time of 0.02 ms; level 2 contains 100,000 words and has an access time of 0.2 ms. Assume that if a word to be accessed is in level 1, then the processor accesses it directly. If it is in level 2, then the word is first transferred to level 1 and then accessed by the processor. For simplicity, we ignore the time required for the processor to determine whether the word is in level 1 or level 2. Suppose 90% of the memory accesses are found in level 1. Then what are the average time to access a word?
b) Consider the execution of a program that results in the execution of 2 million instructions on a 400-MHz processor. The program consists of four major types of instructions. The instruction mix and the CPI for each instruction type are given below, based on the result of a program trace experiment:
Instruction Type CPI Instruction Mix (%)
Arithmetic and logic 1 58
Load/store with cache hit 3 20
Branch 5 10
Memory reference
with cache miss 6 12
Find the average CPI when the program is executed on a uniprocessor with the above descriptions. Also, find MIPS rate.
3. a) Suppose that the processor has access to two levels of memory. Level 1 contains 1000 words and has an access time of 0.02 ms; level 2 contains 100,000 words and has an access time of 0.2 ms. Assume that if a word to be accessed is in level 1, then the processor accesses it directly. If it is in level 2, then the word is first transferred to level 1 and then accessed by the processor. For simplicity, we ignore the time required for the processor to determine whether the word is in level 1 or level 2. Suppose 90% of the memory accesses are found in level 1. Then what are the average time to access a word?
b) Consider the execution of a program that results in the execution of 2 million instructions on a 400-MHz processor. The program consists of four major types of instructions. The instruction mix and the CPI for each instruction type are given below, based on the result of a program trace experiment:
Instruction Type CPI Instruction Mix (%)
Arithmetic and logic 1 58
Load/store with cache hit 3 20
Branch 5 10
Memory reference
with cache miss 6 12
Find the average CPI when the program is executed on a uniprocessor with the above descriptions. Also, find MIPS rate.
(4+4+2)
4. a) Express the (-5.75)10 number in IEEE 32-bit floating point format.
b) The (1 10000011 11000000000000000000000)2 number use the IEEE 32-bit floating-point format. What is the equivalent decimal value?
c) Consider a single-platter disk with the following parameters: rotational speed: 7200 rpm; number of tracks on one side of platter: 30,000; number of sectors per track: 600; seek time: one ms for every hundred tracks traversed. Let the disk receive a request to access a random sector on a random track and assume the head starts at track 0.
i) What is the average seek time?
ii) What is the average rotational latency?
iii) What is the transfer time for a sector?
iv) What is the total average time to satisfy a request?
4. a) Express the (-5.75)10 number in IEEE 32-bit floating point format.
b) The (1 10000011 11000000000000000000000)2 number use the IEEE 32-bit floating-point format. What is the equivalent decimal value?
c) Consider a single-platter disk with the following parameters: rotational speed: 7200 rpm; number of tracks on one side of platter: 30,000; number of sectors per track: 600; seek time: one ms for every hundred tracks traversed. Let the disk receive a request to access a random sector on a random track and assume the head starts at track 0.
i) What is the average seek time?
ii) What is the average rotational latency?
iii) What is the transfer time for a sector?
iv) What is the total average time to satisfy a request?
(3+3+4)
5. a) Write down the steps of Booth’s Algorithm for twos complememt multiplication using flowchart.
b) Use the Booth algorithm to multiply (23)10(multiplicand) by (29)10(multiplier), where each number is represented using 6-bits.
5. a) Write down the steps of Booth’s Algorithm for twos complememt multiplication using flowchart.
b) Use the Booth algorithm to multiply (23)10(multiplicand) by (29)10(multiplier), where each number is represented using 6-bits.
(5+5)
6. a) For a system with two levels of cache, define Tc1 = first - level cache access time; Tc2 = second - level cache access time; Tm = memory access time; H1 = first – level cache hit ratio; H2= combined first/second level cache hit ratio. Provide an equation for Ta for a read operation.
b) Assume a instruction pipeline with six-stages: Fetch Instruction(FI), Decode Instuction(DI), Calculate Operands(CO), Fetch Operands(FO), Execute Instruction(EI), Write Operand(WO). Draw a timing diagram for nine-instructions pipeline operation.
c) Find speeup factor for the instruction pipeline compare to execution without the pipeline.
6. a) For a system with two levels of cache, define Tc1 = first - level cache access time; Tc2 = second - level cache access time; Tm = memory access time; H1 = first – level cache hit ratio; H2= combined first/second level cache hit ratio. Provide an equation for Ta for a read operation.
b) Assume a instruction pipeline with six-stages: Fetch Instruction(FI), Decode Instuction(DI), Calculate Operands(CO), Fetch Operands(FO), Execute Instruction(EI), Write Operand(WO). Draw a timing diagram for nine-instructions pipeline operation.
c) Find speeup factor for the instruction pipeline compare to execution without the pipeline.
(2+4+4)
7. a) What is the memory mapping functions? What are the differences among direct and associative memory mapping function?
b) A set associative cache consists of 64 lines, or slots, divided into four-line sets. Main memory contains 4K blocks of 128 words each. Show the format of main memory addresses.
7. a) What is the memory mapping functions? What are the differences among direct and associative memory mapping function?
b) A set associative cache consists of 64 lines, or slots, divided into four-line sets. Main memory contains 4K blocks of 128 words each. Show the format of main memory addresses.
(4+6)
8. Short notes: (2 x 5)
Answer any two of the following:
8. Short notes: (2 x 5)
Answer any two of the following:
a) Flynn’s taxonomy of processor.
b) RISC versus CISC Architecture.
c) Redundant Array of Independent Disks (RAID).
d) The Memory Hierarchy.
.png)
No comments:
Post a Comment